Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

ABSTRACT

A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

RELATED APPLICATION

This application is a continuation-in-part (CIP) application ofco-pending and co-assigned U.S. Ser. No. 10/448,947, filed May 30, 2003,which application is related to co-pending and co-assigned U.S. patentapplication Ser. No. 10/055,138, filed Jan. 23, 2002, entitled “Methodof Creating High-Quality Relaxed SiGe-On-Insulator for Strained Si CMOSApplications”. The entire contents of each of these related applicationsare incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a method of fabricating a semiconductorsubstrate material, and more particularly to a method of fabricating asubstantially relaxed, high-quality SiGe alloy crystal layer over aninsulating layer by combining aspects of silicon-on-insulator (SOI)formation with the interdiffusion of a Ge-containing layer. The methodof the present invention provides substantially relaxed, high-qualitySiGe-on-insulator substrate materials that can be used as a latticemismatched template for creating a strained Si layer thereon bysubsequent Si epitaxial overgrowth. Such strained Si layers have highcarrier mobility and are useful in high-performance complementary metaloxide semiconductor (CMOS) applications. The present invention is alsodirected to SiGe-on-insulator substrate materials as well as structuresthat include at least the SiGe-on-insulator substrate material.

The present invention also provides a silicon germanium-on-insulator(SGOI) substrate having the necessary properties required for use inmodern CMOS IC manufacturing. For instance, Ge atoms can diffuse througha poorly formed buried diffusion barrier and thus conditions must bechosen to form a continuous layer as early in the anneal as possible tominimize Ge loss into the underlying substrate. The surface of SiGealloys tends to form pits at high oxidation temperatures (>1250° C.)which need to be minimized. It is also important that the diffusionbarrier layer formed be of a sufficient electrical quality to be usefulin CMOS processing. The SiGe crystal defects need to be minimized toensure that the operation of devices formed thereon is not compromised.The present invention thus also provides optimized conditions whichaddress the aforementioned challenges.

BACKGROUND OF THE INVENTION

In the semiconductor industry, silicon-on-insulator substrates may beformed using a process referred to in the art as separation by ionimplantation of oxygen (SIMOX). In a SIMOX process, a Si wafer isimplanted with oxygen at high doses (on the order of 5E16 atoms/cm² orgreater) and then annealed and oxidized at very high temperatures (onthe order of about 1300° C. or greater) to form a well-defined andcontinuous buried oxide layer below the surface of the Si wafer. Thehigh-temperature anneal serves both to chemically form the buried oxidelayer as well as to annihilate any defects that persist in thenear-surface silicon layer by annealing near the melting point ofsilicon.

Because of the recent high-level of activity using strained Si-basedheterostructures, there is a need for providing SiGe-on-insulator (SGOI)substrates in which the SiGe layer is substantially relaxed and ofhigh-quality. SGOI substrates may be formed using various processesincluding, for example, the SIMOX process. In the prior art, a thickSiGe layer having a thickness of about 1 to about 5 micrometers is firstdeposited atop a Si wafer and then the SIMOX process is performed. Sucha prior art process suffers the following two drawbacks: 1) the Ge tendsto diffuse into the bulk before a continuous oxide layer is formed and2) the presence of Ge near the O peak inhibits the formation of ahigh-quality buried oxide layer unless the Ge concentration is very low.

In view of the drawbacks with prior art SIMOX processes of forming aSGOI substrate material, there is a need for providing a new andimproved SIMOX method that reduces the tendency of Ge to diffuse intobulk Si before a continuous buried insulating layer is formed andprovides a relaxed, high-quality SiGe alloy layer atop a buriedinsulating layer.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a method offabricating thin, high-quality, substantially relaxed SiGe-on-insulatorsubstrate materials.

Another object of the present invention is to provide a method offabricating thin, high-quality, substantially relaxed SiGe-on-insulatorsubstrate materials that are stable against further defect productionsuch as misfit and threading dislocations.

A further object of the present invention is to provide a method offabricating thin, high-quality, substantially relaxed SiGe-on-insulatorsubstrate materials that is compatible with CMOS processing steps.

A yet further object of the present invention is to provide a method offabricating thin, high-quality, substantially relaxed SiGe-on-insulatorsubstrate materials which can then be used as lattice mismatchedtemplates, i.e., substrates, for forming strained Si-containing layers.

A still further object of the present invention is to provide strainedSi/substantially relaxed SiGe-on-insulator structures that have highcarrier mobility and are useful in high-performance CMOS applications.

An even further object of the present invention is to provide a methodof fabricating a substantially relaxed, high-quality SiGe alloy crystallayer over an insulating layer by combining aspects ofsilicon-on-insulator (SOI) formation with the interdiffusion of aGe-containing layer.

Another object of the present invention is to provide a method offabricating a substantially relaxed, high-quality SiGe-on-insulatorsubstrate material that takes advantage of the defect annihilationproperties of a SIMOX anneal, while allowing the formation of asubstantially relaxed, high-quality SiGe alloy crystal layer over aburied insulating layer that is highly resistant to Ge diffusion.

A still other object of the present invention is to provide optimizedconditions for fabricating a high-quality SiGe-on-insulator substratematerial which are capable of (1) providing sufficient electricalquality to the diffusion barrier layer; (2) minimizing Ge loss; (3)minimizing surface pit formation in the SiGe alloy layer, and (4)minimizing SiGe crystal defects.

These and other objects and advantages are achieved in the presentinvention by utilizing a method that includes first implanting ions,such as oxygen ions, into a Si-containing substrate to form animplanted-ion rich (which can also be referred to as an implant richregion) region in the Si-containing substrate. The implanted-ion richregion has a sufficient ion concentration such that during a subsequentanneal at high temperatures a barrier layer that is resistant to Gediffusion is formed. Next, a Ge-containing layer, such as SiGe or pureGe, is formed on a surface of the Si-containing substrate, andthereafter a heating step is performed at a temperature which permitsformation of the barrier layer and interdiffusion of Ge thereby forminga substantially relaxed, single crystal SiGe layer atop the barrierlayer. It is noted that the substantially relaxed, single crystal layeris comprised of a homogeneous mixture of at least the SiGe or pure Gelayer and part of the Si-containing substrate that exists above theimplanted-ion rich region.

Following these steps of the present invention, a strained Si-containinglayer may be grown epitaxially atop the substantially relaxed singlecrystal SiGe layer to form a strained Si-containing/relaxedSiGe-containing heterostructure that can be used in a variety ofhigh-performance CMOS applications.

The present method also contemplates forming barrier layers that areunpatterned (i.e., barrier layers that are continuous) or patterned(i.e., discrete and isolated barrier regions or islands which aresurrounded by semiconductor material).

In yet another embodiment of the present invention, a Si-containing caplayer is formed atop the Ge-containing layer prior to heating thestructure. This embodiment of the present invention alters thethermodynamic stability of the SiGe layer in order to prevent defectproduction during annealing. The SiGe layer has a thickness of about2000 nm or less, with a thickness from about 10 to about 200 nm beingmore highly preferred.

In another embodiment of the present invention, a Si-containing “buffer”layer is formed atop the Si-containing substrate prior to formation ofthe Ge-containing layer. This embodiment provides an alternate method ofcontrolling the depth of the implanted-ion rich region below thesurface. The Si-containing buffer layer has a thickness greater than 10nm, with a thickness of from about 20 to 2000 nm being more highlypreferred.

In still another embodiment of the present invention, optimal conditionsfor the implant step and heating step are provided which are capable offorming a high-quality SGOI substrate material that is of a sufficientelectrical quality to be useful in modern CMOS applications whereby thesubstrate exhibits minimized Ge loss; minimized surface pit formation;and minimized SiGe crystal defects. Specifically, and in this embodimentof the present invention, applicants have determined the optimal implantconditions, SiGe growth conditions, thermal annealing/oxidationconditions and post thermal processing conditions that provide ahigh-quality SGOI substrate material. The post thermal processingconditions include a non-selective thinning step that thins the SiGealloy layer to a desired thickness, while reducing the number of surfacepit defects that are present in the SiGe alloy layer.

Another aspect of the present invention relates to the SiGe-on-insulatorsubstrate material that is formed utilizing the above-mentionedprocessing steps. Specifically, the inventive substrate materialcomprises a Si-containing substrate; an insulating region that isresistant to Ge diffusion present atop the Si-containing substrate; anda substantially relaxed SiGe layer present atop the insulating region,wherein the substantially relaxed SiGe layer has a thickness of about2000 nm or less. A characteristic feature of the inventiveSiGe-on-insulator substrate material is that it has a defect densitythat is typical of contemporary SGOI material. Specifically, theSiGe-on-insulator substrate material of the present invention has ameasured defect density of about 5×10⁷ cm⁻² or less.

A yet further aspect of the present invention relates to aheterostructure which includes at least the above-mentioned substratematerial. Specifically, the heterostructure of the present inventioncomprises a Si-containing substrate; an insulating region that isresistant to Ge diffusion present atop the Si-containing substrate; asubstantially relaxed SiGe layer present atop the insulating region,wherein the substantially relaxed SiGe layer has a thickness of about2000 nm or less; and a strained Si-containing layer formed atop thesubstantially relaxed SiGe layer.

Other aspects of the present invention relate to superlattice structuresas well as templates for other lattice mismatched structures whichinclude at least the SiGe-on-insulator substrate material of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are pictorial representations (through cross-sectionalviews) showing the basic processing steps that are employed in thepresent invention in fabricating a thin, high-quality, substantiallyrelaxed SiGe-on-insulator substrate material. In these drawings, acontinuous, i.e., unpatterned, barrier layer that is resistant to Gediffusion is formed.

FIGS. 2A-2D are pictorial representations (through cross-sectionalviews) showing the basic processing steps that are employed in analternative embodiment of the present invention in fabricating a thin,high-quality, substantially relaxed SiGe-on-insulator substratematerial. In these drawings, a patterned barrier layer that is resistantto Ge diffusion is formed.

FIGS. 3A-3B are pictorial representations (through cross-sectionalviews) showing an alternative embodiment of the present inventionwherein a Si cap layer is formed atop a Ge-containing layer which isformed on the structure shown in FIG. 1B or the structure shown in FIG.2B.

FIGS. 4A-4B are pictorial representations (through cross-sectionalviews) showing the formation of a strained Si-containing layer on thethin, high-quality, substantially relaxed SiGe-on-insulator substratematerial of FIGS. 1D and 2D, respectively.

FIG. 5 is a SEM of a SiGe-on-insulator substrate material formed usingthe processing steps of the present invention.

FIGS. 6A-6B are SEMs of a SiGe-on-insulator substrate material formedusing the optimal conditions described in the Example.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a method of fabricating thin,high-quality, substantially relaxed SiGe-on-insulator substratematerials which can then serve as a lattice mismatched template forsubsequent overgrowth of an epitaxial Si-containing layer, will now bedescribed in greater detail by referring to the drawings the accompanythe present application. In the accompanying drawings, like and/orcorresponding elements are referred to by like reference numerals. It isalso noted that the following description will describe the optimalconditions that can be used in forming a high-quality SiGe-on-insulatorsubstrate material whereby the electrical quality of the diffusionbarrier is improved, while minimizing: (i) surface pits in the SiGealloy layer, (ii) Ge loss, and (iii) SiGe crystal defects.

Reference is first made to FIGS. 1A-1D which illustrate the basicprocessing steps of the present invention. Specifically, FIG. 1A showsthe first processing step of the present invention in which ions 12 areimplanted into a Si-containing substrate 10 so as to form animplanted-ion rich region 14 in the Si-containing substrate 10. Theimplanted-ion rich region 14 may be simply referred to as an implantrich region 14. As illustrated, the implanted-ion rich region 14 islocated beneath a surface layer of Si-containing substrate 10. The term“Si-containing” as used herein denotes a semiconductor substrate thatincludes at least silicon. Illustrative examples include, but are notlimited to: Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC, and preformedsilicon-on-insulators which may include any number of buried oxide(continuous, non-continuous or mixtures of continuous andnon-continuous) regions present therein.

The ions 12 that are implanted into the Si-containing substrate 10 atthis point of the present invention are any ions that are capable offorming a barrier layer that is resistant to Ge diffusion when subjectedto a subsequent heating step. Illustrative examples of such ionsinclude, but are not limited to: oxygen ions, nitrogen ions, NO ions,inert gases and mixtures thereof. Preferred ions 12 that are implantedinto the Si-containing substrate 10 at this point of the presentinvention are atomic or molecular oxygen ions.

The ions 12 are implanted into the Si-containing substrate 10 in asufficient concentration that forms an implanted-ion rich region 14 inthe Si-containing substrate. The implanted-ion rich region 14 formed atthis point of the present invention has an ion concentration that issufficient to form a barrier layer resistant to Ge diffusion in theSi-containing substrate when subjected to a subsequent heating step.Typically, the implanted-ion rich region 14 formed in this step of thepresent invention has an ion concentration of about 1×10²² atoms/cm³ orgreater.

The implanted-ion rich region 14 is formed below the upper surface ofSi-containing substrate 10 such that a surface layer of Si-containingmaterial lies atop the implanted-ion rich region 14. Typically, theimplanted-ion rich region 14 is formed about 50 nm or greater below theupper surface of the Si-containing substrate 10.

The ions 12 are implanted using SIMOX processes and conditions that arewell known to those skilled in the art, as well as the various SIMOXprocesses and conditions mentioned in co-assigned U.S. patentapplication Ser. No. 09/861,593, filed May 21, 2001; Ser. No.09/861,594, filed May 21, 2001; Ser. No. 09/861,590, filed May 21, 2001;Ser. No. 09/861,596, filed May 21, 2001; and Ser. No. 09/884,670, filedJun. 19, 2001 as well as U.S. Pat. No. 5,930,634 to Sadana, et al., theentire contents of each are being incorporated herein by reference. Theimplant may be a blanket implant as shown in FIG. 1A or a patternedimplant as shown in FIG. 2A may be employed. The patterned implant mayinclude a mask formed directly on the upper surface of the Si-containingsubstrate 10 or a mask that is located some distance from the uppersurface of the Si-containing substrate 10 may be employed.

Although various implant conditions can be employed in the presentinvention, the following provides general implant conditions for formingan implanted-ion rich region 14 in the Si-containing substrate 10:

I. High-dose ion implantation: The term “high-dose” as used hereindenotes an ion dosage of about 4E17 cm⁻² or greater, with an ion dosagefrom about 4E17 to about 2E18 cm⁻² being more preferred. In addition tousing high-ion dosage, this implant is typically carried out in an ionimplantation apparatus that operates at a beam current density fromabout 0.05 to about 500 milliamps cm⁻² and at an energy from about 50 toabout 1000 keV. More preferably, this implant is carried out using anenergy from about 150 to about 210 keV.

This implant, which may be referred to as a base ion implant, is carriedout at a temperature from about 200° C. to about 800° C. at a beamcurrent density from about 0.05 to about 500 mA cm⁻². More preferably,the base ion implant may be carried out at a temperature from about 200°C. to about 600° C. at a beam current density from about 5 to about 10mA cm^(−2.)

If desired, the base ion implant step may be followed by a second oxygenimplant that is carried out using an ion dose from about 1E14 to about1E16 cm⁻², with an ion dose from about 1E15 to about 4E15 cm⁻² beingmore highly preferred. The second ion implant is carried out at anenergy of from about 40 keV or greater, with an energy from about 120 toabout 450 keV being more preferred.

This second implant is performed at a temperature from about 4K to about200° C. with a beam current density from about 0.05 to about 10 mA cm⁻².More, preferably, the second ion implant may be performed at atemperature from about 25° C. to about 100° C. with a beam currentdensity from about 0.5 to about 5.0 mA cm^(−2.)

Note that the second ion implant forms an amorphous region that isshallower the damaged region caused by the base ion implant step. Duringthe subsequent heating step of the present invention, the amorphous anddamaged region become part of a barrier layer that is resistant to Gediffusion.

II. Low-dose ion implant: The term “low-dose” as used herein for thisembodiment of the present invention denotes an ion dose of about 4E17cm⁻² or less, with an ion dose from about 1E16 to about 3.9E17 cm⁻²being more preferred. This low-dose implant is performed at an energyfrom about 40 to about 10000 keV, with an implant energy from about 40to about 210 keV being more highly preferred.

This implant, which may be referred to as a base ion implant, is carriedout at a temperature from about 100° C. to about 800° C. Morepreferably, the base ion implant may be carried out at a temperaturefrom about 200° C. to about 650° C. with a beam current density fromabout 0.05 to about 500 mA cm⁻².

The low-dose base implant step is preferably followed by a second ionimplant that is carried out using the conditions mentioned above.

It is again emphasized that the above types of implant conditions areexemplary and by no way limit the scope of the present invention.Instead, the present invention contemplates all conventional ionimplants that are typically employed in conventional SIMOX processes.

In a preferred embodiment of the present invention, a low-dose oxygenion implant step is performed utilizing the following optimal conditionsfor the base ion implant step and the second ion implant step. In thisembodiment of the present invention, oxygen ions are implanted into theSi-containing substrate 10 using a base ion implant step and a secondion implant step. Specifically, the base oxygen ion implant step isperformed at an optimal energy from about 100 to about 220 keV and at anoptimal dose from about 1.5E17 to about 3E17 cm⁻². More preferably, thebase oxygen ion implant step is performed at an optimal energy fromabout 150 to about 175 keV and at an optimal dose from about 1.8E17 toabout 2.75E17 cm⁻².

Other optimal conditions for the base oxygen implant step include: animplant temperature from about 200° C. to about 600° C., with a baseoxygen implant temperature from about 200° C. to about 450° C. beingmore highly preferred. The optimal beam current density for the baseoxygen implant step is from about 0.01 to about 0.1 mA cm⁻².

After performing the base oxygen implant step using the aforementionedoptimal implant conditions, a second oxygen implant step, which isperformed at a lower temperature than the base oxygen implant step, isemployed. The second oxygen implant step is performed at an optimalenergy from about 100 to about 220 keV at an optimal oxygen dose fromabout 1E15 to about 3E15 cm⁻². More preferably, the second oxygenimplant step is performed at optimal energy from about 150 to about 170keV at an optimal oxygen dose from about 2E15 to about 2.75E15 cm⁻².

The second oxygen implant is performed at an optimal implant temperaturefrom about −200° C. to about 150° C., with an optimal implanttemperature from about 20° C. to about 100° C. being more highlypreferred. The optimal beam current density for the second oxygenimplant step is from about 0.001 to about 0.1 mA cm⁻².

Using the optimal conditions mentioned above, the second oxygen implantforms an amorphous region that is shallower than the damaged regioncreated by the optimal base oxygen implant step. That is, the secondimplant displaces the peak of the implant closer to the surface of thesubstrate than the base implant. Specifically, the amorphous regioncreated by the second oxygen implant steps is from about 0 to about 500Å shallower than the damaged region created by the base oxygen implantstep. More specifically, the amorphous region is about 150 to about 250Å shallower than the damaged region created by the base oxygen implantstep.

It again emphasized that the aforementioned optimal implant conditionsare used in a preferred embodiment of the present invention to provide ahigh-quality SiGe-on-insulator substrate material. It is noted that thelow-dose implant regime is preferred over the high-dose implant regimesince the low-dose regime provides a higher quality thermal oxide ascompared to oxide formed from implanted oxygen. Moreover, the low-doseregime provides a diffusion barrier in the final SiGe-on-insulatorsubstrate material that exhibits a mini-breakdown voltage that is lessthan that of a diffusion barrier provided by a high-dose implant regime.In the case wherein the optimal conditions are employed, the diffusionbarrier is a buried oxide having a mini-breakdown electric field ofabout 6 MV/cm or more.

In some embodiments (not shown), a Si-containing buffer layer is formedatop the Si-containing substrate 10 prior to formation of theGe-containing layer 16. This particular embodiment provides analternative method for controlling the depth of the implanted-ion richregion 12 below the surface. When employed, the Si-containing bufferlayer has a thickness greater than 10 nm, with a thickness from about 20to 2000 nm being more preferred.

FIG. 1B illustrates the structure that is formed after a Ge-containinglayer 16 is formed atop the upper surface of Si-containing substrate 10.The Ge-containing layer 16 formed at this point of the present inventionmay be a SiGe alloy layer or a pure Ge layer. The term “SiGe alloylayer” includes SiGe alloys that comprise up to 99.99 atomic percent Ge,whereas pure Ge includes layers that comprise 100 atomic percent Ge.When SiGe alloy layers are employed, it is preferred that the Ge contentin the SiGe alloy layer be from about 0.1 to about 99.9 atomic percent,with a Ge atomic percent of from about 10 to about 35 being even morehighly preferred.

In accordance with the present invention, the Ge-containing layer 16 isformed atop an upper surface of the Si-containing substrate 10 using anyconventional epitaxial growth method that is well known to those skilledin the art which is capable of (i) growing a thermodynamically stable(below a critical thickness) SiGe alloy or pure Ge layer, (ii) growing aSiGe alloy or pure Ge layer that is metastable and free from defects,i.e., misfit and TD dislocations, or (iii) growing a partially or fullyrelaxed SiGe layer; the extent of relaxation being controlled by growthtemperature, Ge concentration, thickness, or the presence of a Sicapping layer.

Illustrative examples of such epitaxial growing processes that arecapable of satisfy conditions (i), (ii) or (iii) include, but are notlimited to: low-pressure chemical vapor deposition (LPCVD), ultra-highvacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemicalvapor deposition (APCVD), molecular beam (MBE) epitaxy andplasma-enhanced chemical vapor deposition (PECVD).

In some embodiments of the present invention, it is desirable to formSiGe layers with a reduced variation in isotopic masses. This can beaccomplished by growing epitaxial SiGe layers from a Ge source that issubstantially composed of ⁷⁴Ge, for example: Other Ge sources include⁷⁰Ge, ⁷²Ge, ⁷³Ge or ⁷⁶Ge. SiGe layers with reduced isotopic massvariation have improved thermal conductivity compared to equivalentlayers with a naturally occurring distribution of isotopic mass.

The thickness of the Ge-containing layer 16 formed at this point of thepresent invention may vary, but typically the Ge-containing layer 16 hasa thickness from about 10 to about 500 mm, with a thickness from about20 to about 200 nm being more highly preferred.

In another embodiment of the present invention, the optimal conditionsfor growing the Ge-containing layer 16 include a thickness from about 50to about 500 nm, with a thickness from about 100 to about 200 mm beingmore highly preferred. The optimal Ge content in the Ge-containing layer16 is within the range from about 5 to about 40 atomic percent, with anoptimal Ge content from about 15 to about 25 atomic percent being morehighly preferred.

In an alternative embodiment of the present invention, see FIGS. 3A-3B,optional cap layer 18 is formed atop Ge-containing layer 16 prior toperforming the heating step of the present invention. The optional caplayer employed in the present invention comprises any Si orSi-containing material including, but not limited to: epitaxial silicon(epi-Si), epitaxial silicon-germanium (epi-SiGe), amorphous silicon(a:Si), amorphous silicon-germanium (a:SiGe), single or polycrystallineSi or any combination thereof including multilayers. In a preferredembodiment, the cap layer 18 is comprised of epi Si. It is noted thatlayers 16 and 18 may, or may not, be formed in the same reactionchamber.

When present, optional cap layer 18 has a thickness from about 1 toabout 100 nm, with a thickness from about 1 to about 30 nm being morehighly preferred. The optional cap layer 18 is formed utilizing anywell-known deposition process including the epitaxial growth processesmentioned above.

In one embodiment of the present invention, it is preferred to form apure Ge or SiGe alloy (15 to 20 atomic percent Ge) layer 16 having athickness from about 1 to about 2000 nm on the surface of theSi-containing substrate 10, and thereafter form a Si cap layer 18 havinga thickness from about 1 to about 100 nm atop the Ge or SiGe layer.

After forming the Ge-containing layer 16 (and optional cap layer 18)atop the implanted Si-containing substrate, the substrate is thenheated, i.e., annealed, at a temperature which permits interdiffusion ofGe throughout the surface Si-containing layer, Ge-containing layer 16and, if present, the optional Si cap 18 thereby forming substantiallyrelaxed, single crystal SiGe layer 20 atop a barrier layer 22 that isalso formed during the heating step. FIG. 1C shows the resultantstructure that is formed after the heating step of the present inventionhas been performed. Note that oxide layer 24 is formed atop layer 20during the heating step. This oxide layer is typically, but not always,removed from the structure after the heating step using a conventionalwet etch process wherein a chemical etchant such as HF that has a highselectivity for removing oxide as compared to SiGe is employed.

Note that when the oxide layer is removed, a single crystal Si layer canbe formed atop layer 20 and the above processing steps of the presentinvention may be repeated any number of times to produce a multilayeredrelaxed SiGe substrate material.

The oxide layer 24 formed after the heating step of the presentinvention has a variable thickness which may range from about 10 toabout 1000 nm, with a thickness from about 100 to about 900 nm beingmore highly preferred.

Specifically, the heating step of the present invention is an annealingstep that is performed at a high temperature from about 900° C. to about1350° C., with a temperature from about 1200° C. to about 1335° C. beingmore highly preferred. Moreover, the heating step of the presentinvention is carried out in an oxidizing ambient which includes at leastone oxygen-containing gas such as O₂, NO, N₂O, ozone, air and other likeoxygen-containing gases. The oxygen-containing gas may be admixed witheach other (such as an admixture of O₂ and NO), or the gas may bediluted with an inert gas such as He, Ar, N₂, Xe, Kr, or Ne.

The heating step may be carried out for a variable period of time thattypically ranges from about 10 to about 1800 minutes, with a time periodfrom about 60 to about 600 minutes being more highly preferred. Theheating step may be carried out at a single targeted temperature, orvarious ramp and soak cycles using various ramp rates and soak times canbe employed.

The heating step is performed under an oxidizing ambient to achieve thepresence of a surface oxide layer, i.e., layer 24, which acts as adiffusion barrier to Ge atoms. Therefore, once the oxide layer 24 isformed on the surface of the structure, Ge becomes trapped betweenbarrier layer 22 and oxide layer 24. As the surface oxide increases inthickness, the Ge becomes more uniformly distributed throughout layers14, 16, and optionally 18, but it is continually and efficientlyrejected from the encroaching oxide layer. So as the (now homogenized)layers are thinned during this heating step, the relative Ge fractionincreases. Efficient thermal mixing is achieved in the present inventionwhen the heating step is carried out at a temperature from about 1200°C. to about 1320° C. in a diluted oxygen-containing gas.

It is also contemplated herein to use a tailored heat cycle that isbased upon the melting point of the SiGe layer. In such an instance, thetemperature is adjusted to tract below the melting point of the SiGelayer.

Note that if the oxidation occurs too rapidly, Ge cannot diffuse awayfrom the surface oxide/SiGe interface fast enough and is eithertransported through the oxide (and lost) or the interfacialconcentration of Ge becomes so high that the alloy melting temperaturewill be reached.

The role of the high-temperature heating step of the present inventionis (1) to form a barrier layer 22 that is resistant to Ge diffusion inthe Si-containing substrate: (2) to allow Ge atoms to diffuse morequickly thereby maintaining a homogeneous distribution during annealing;and (3) to subject the initial layered structure to a thermal budgetwhich will facilitate an equilibrium configuration. After this heatingstep has been performed, the structure includes a uniform andsubstantially relaxed SiGe alloy layer, i.e., layer 20, located betweenthe barrier layer 22 and surface oxide layer 24.

In another preferred embodiment of the present invention, the finalheating step in the oxidizing ambient is not performed above 1250° C.The reasons for limiting the heating in the oxidizing ambient to atemperature below 1250° C. are to minimize surface pit formation andmaintain low stacking fault defect density (less than about 10⁶defects/cm² depending on the final SiGe thickness). In this preferredembodiment of the present invention, the applicants have determined theoptimal conditions that are necessary for providing a high-qualitySiGe-on-insulator substrate in which Ge loss, surface pit formation andcrystal defects are substantially minimized.

In broad terms, the optimal conditions for the heating step of thepresent invention include the following steps:

-   -   (i) first ramping up the substrate containing implanted oxygen        and at least the Ge-containing layer in an oxygen-containing gas        to a first temperature that is sufficient to initiate formation        of a buried oxide region in said substrate, while substantially        avoiding slip generation;    -   (ii) first soaking at the first temperature to form a continuous        buried oxide in said substrate;    -   (iii) second ramping up in an oxygen-containing gas from the        first temperature to a second temperature that is sufficient to        increase the thickness of the buried oxide in said substrate;    -   (iv) second soaking at said second temperature to increase and        control thermal oxide thickness and to provide a sharpened        interface between the SiGe layer and the buried oxide;    -   (v) ramping down from the second temperature to a third        temperature that is less than or equal to the melting point of a        final desired Ge concentration, while allowing Ge diffusion for        concentration homogenization; and    -   (vi) oxidizing at said third temperature to provide a SiGe alloy        layer having said final Ge content and a thickness that is        sufficient to minimize stacking faults.

In steps (iii) and (v) the conditions are also capable of substantiallyavoiding slip generation.

As indicated above, the first step of the optimal heating step includesa first ramp up cycle. The first ramp up cycle is performed underconditions in which slip generation is substantially avoided, whileinitiating the formation of a buried oxide in the substrate. The buriedoxide at this step of the optimal heating step is composed mainly ofoxide that is generated from implanted oxygen. The first ramp up cyclemay begin at room temperature or at an initial substrate temperaturethat is higher than room temperature such as, for example, a temperaturefrom about 800° C. to about 1150° C. In the case when the initialsubstrate temperature is higher than room temperature, an initialheating step in an inert atmosphere such as, for example, He or Ar, isemployed. The first ramp up cycle is performed in the presence of anoxygen-containing gas, i.e., ambient, such as one of theoxygen-containing gases mentioned above. The oxygen-containing gas maybe diluted with an inert gas such that the concentration ofoxygen-containing gas in the admixture is from about 0.5 to about 10%.An example of an oxygen-containing gas that is employed during the firstramp up cycle is 1.5%.

The first ramp up cycle is performed by heating the substrate from theinitial temperature to a first temperature that is in the range fromabout 1275° C. to about 1320° C. More preferably, the first ramp upcycle is performed until a first temperature from about 1280° C. toabout 1310° C. is obtained. The rate for the first ramp up cycle is lessthan or equal to 1° C./min.

After the first ramp up cycle is completed, a first soak cycle isperformed at the first temperature achieved by the first ramp up cycle.That is, a soak cycle is performed at a temperature from about 1275° C.to about 1320° C. The first soak cycle is performed in a gas ambientthat is the same or substantially the same as the first ramp up cycle.The first soak is performed for a time period from about 0.5 to about 5hours, with a time period from about 1 to about 2 hours being morehighly preferred.

The foregoing conditions for the first soak cycle, which may also bereferred to a first annealing cycle, are sufficient to complete theformation of a continuous buried oxide in the substrate.

After the first soak cycle, a second ramp up cycle is performed. Thesecond ramp up cycle is carried out from the first temperature of thefirst soak cycle to a second temperature which is from about 1315° C. toabout 1335° C. More preferably, the second ramp up is performed until asecond temperature from about 1320° C. to about 1330° C. is obtained.The rate for the second ramp up cycle is less than or equal to 1°C./min. The second ramp up cycle is performed in an oxygen-containinggas that is typically admixed with an inert gas. For example, the secondramp up cycle may be performed in an admixture of 10% or greateroxygen-containing gas and 90% or less inert gas. In one preferredembodiment, the second ramp up is performed in 50% oxygen and 50% Ar.

During the second ramp up cycle, the conditions are selected such thatthe thickness of the buried oxide layer increases. The thickness of theburied oxide is increased by an internal thermal oxidation process. Asknown to those skilled in the art, thermal oxides typically are ofbetter quality than oxides that are formed from implanted oxygen.

Thus, a second soak cycle at the temperature range mentioned above isemployed in the present invention to increase the thickness of thethermal oxide formed. In addition to increasing the thickness of thethermal oxide formed, the second soak cycle also helps to sharpen theinterface between the buried oxide and the overlying SiGe layer thatalso begins to form via Ge diffusion and homogenization. The term“sharpen” is used in the present invention to denote that during thisstep of the present invention the interface between the buried oxide andthe overlying SiGe alloy becomes planarized, i.e., the waviness of theinterface is substantially minimized.

The second soak cycle is typically performed in the same orsubstantially the same ambient as the second ramp up cycle. The secondsoak cycle is performed for a time period from about 1 to about 10hours, with a time period from about 3 to about 6 hours being morehighly preferred.

After completion of the second soak cycle, a ramp down cycle isperformed. The ramp down cycle is performed from the second temperatureof the second soak cycle to a third temperature that is at or below themelting point of the final desired SiGe concentration, while stillallowing Ge diffusion for alloy homogenization. Specifically, the rampdown is performed to a temperature that is from about 1350° C. to about1150° C., with a temperature from about 1300° C. to about 1200° C. beingmore highly preferred. The third temperature achieved by the ramp downcycle is dependent on the final Ge concentration in the SiGe layer.

The ramp down cycle can be performed at a rate that is less than orequal to 1° C./min. The ramp down cycle is performed in the same orsubstantially the same ambient as the second soak cycle or in an inertambient.

After completion of the ramp down cycle, the substrate is oxidized ineither the same or substantially the same ambient as the previous cycle,100% oxygen or steam, or under any oxidation conditions that aresufficient to obtain a final Ge fraction in the SiGe alloy layer, yetprovide a SiGe alloy layer that is thick enough to minimize stackingfaults. Specifically, the oxidizing cycle is performed at the thirdtemperature achieved by the ramp down cycle for a time period from about1 to about 10 hours, with a time period from about 1 to about 5 hoursbeing more highly preferred.

The above cycles along with their optimal conditions are used in someembodiments of the present invention to obtain a high-qualitySiGe-on-insulator in which (i) Ge loss is minimized, (ii) pit formationis minimized, and (iii) SiGe crystal defects are minimized.

After performing the oxidation cycle, the substrate is ramped down tonominal room temperature, removed from the heating apparatus and theresulting surface oxide layer 24 is removed as discussed herein. TheSiGe alloy layer 20 of the resultant SiGe-on-insulator substratematerial can then be subjected to a non-selective thinning step. Thenon-selective thinning step is employed in the present invention tofurther remove surface pit defects from the SiGe alloy layer 20.Illustrative examples of non-selective thinning processes that can beemployed in the present invention include, but are not limited to:chemical mechanical polishing (CMP), grinding, high-pressure oxidation,wet etching, steam oxidation, gas-cluster beam thinning and anycombination thereof. In one preferred embodiment, CMP is employed as thenon-selective thinning technique. The surface roughness of the relaxedSiGe layer after the non-selective thinning process is performed istypically about 1.5 nm (RMS) or less.

In accordance with the present invention, the substantially relaxed SiGelayer 20 has a thickness of about 2000 nm or less, with a thickness fromabout 10 to about 100 nm being more highly preferred. The barrier layer22 formed during the annealing step of the present invention has athickness of about 500 nm or less, with a thickness from about 50 toabout 200 nm being more highly preferred. Note that the substantiallyrelaxed SiGe layer 20 formed in the present invention is thinner thanprior art SiGe buffer layers and has a defect density including misfitsand TDs, of less than about 5×10⁷ defects/cm². This defect density valueapproaches those reported for contemporary SGOI materials. When theoptimal conditions are employed, the SiGe layer 20 has a stacking faultdefect density that is about 1000 defects/cm² or less.

The substantially relaxed SiGe layer 20 formed in the present inventionhas a final Ge content from about 0.1 to about 99.9 atomic percent, withan atomic percent of Ge from about 10 to about 35 being more highlypreferred. Another characteristic feature of the substantially relaxedSiGe layer 20 is that it has a measured lattice relaxation from about 1to about 100%, with a measured lattice relaxation from about 50 to about80% being more highly preferred.

As stated above, the surface oxide layer 24 may be stripped at thispoint of the present invention so as to provide the SiGe-on-insulatorsubstrate material shown, for example, in FIG. 2D (note that thesubstrate material does not include the cap layer since that layer hasbeen used in forming the relaxed SiGe layer).

FIGS. 2A-2D show an embodiment of the present invention in which apatterned barrier layer 22 is formed. In this embodiment of the presentinvention, a masked ion implantation step such as shown in FIG. 2A isperformed. In FIG. 2A, reference numeral 15 denotes an implantation maskthat is used in this embodiment of the present invention. Theimplantation mask shown in FIG. 2A is formed using conventionaltechniques well know in the art. Although the implantation mask 15 maybe removed after the implant step shown in FIG. 2A, it may also remainon the structure during the formation of Ge-containing layer 16, SeeFIG. 2B. After forming the Ge-containing layer 16, the mask 15 may beremoved at this point of the present invention. Implantation maskremoval is carried out using conventional stripping processes well knownto those skilled in the art. FIG. 2C shows the structure after theheating step and FIG. 2D shows the structure after removing oxide layer24. Note the implantation mask may remain on the structure throughoutthe entire process.

FIGS. 4A-B show the structure that is obtained after forming aSi-containing layer 26 atop the SiGe layer 20 of FIGS. 1D and 2D,respectively. Si-containing layer 26 is formed using a conventionalepitaxial deposition process well known in the art. The thickness of theepi-Si layer 26 may vary, but typically, the epi-Si layer 26 has athickness of from about 1 to about 100 nm, with a thickness of fromabout 1 to about 30 nm being more highly preferred.

In some instances, additional SiGe can be formed atop the substantiallyrelaxed SiGe layer 20 utilizing the above mentioned processing steps,and thereafter epi-Si layer 26 may be formed. Because layer 20 has alarge in-plane lattice parameter as compared to epi-layer 26, epi-layer26 will be strained in a tensile manner.

As stated above, the present invention also contemplates superlatticestructures as well as lattice mismatched structures which include atleast the SiGe-on-insulator substrate material of the present invention.In the case of superlattice structures, such structures would include atleast the substantially relaxed SiGe-on-insulator substrate material ofthe present invention, and alternating layers Si and SiGe formed atopthe substantially relaxed SiGe layer of the substrate material.

In the case of lattice mismatched structures, GaAs, GaP or other likeIII/V compounds would be formed atop the substantially relaxed SiGelayer of the inventive SiGe-on-insulator substrate material.

It should be noted that any of the foregoing embodiments, i.e.,patterning, epi Si growth, SiGe growth and supperlattice formation canbe used in conjunction with the optimal conditions mentioned above.

FIG. 5 is an actual SEM of a substantially relaxed SiGe-on-insulatorsubstrate material that was formed using the method of the presentinvention (with the surface oxide stripped off). In particular, theSiGe-on-insulator substrate material shown in FIG. 5 was prepared byfirst implanting oxygen ions into a Si-containing wafer using implantconditions that fall within the ranges mentioned above. A 600 Å-17% SiGealloy layer was then grown atop the implanted Si-containing substrateand thereafter a single anneal/oxidation was carried out at 1320° C. ina Ar-O₂ atmosphere. In the image, the top (black) region is the areaabove the sample (SEM chamber). The first light-gray layer is the SGOIlayer, below that is a darker gray band which is the buried oxide layer(BOX) formed during the high-temperature step. The light gray layerbelow the BOX is the Si substrate. X-ray diffraction showed that theSiGe layer (94.2 nm) contained 4 atomic % Ge and was 92% relaxed. Theburied oxide had a thickness of about 47.10 nm and was continuous andwell-formed.

In summary, the SiGe-on-insulator substrate material is formed in thepresent invention as an integrated process that combines the benefits ofthe high temperature SIMOX anneal with the simplicity of the Gediffusion and segregation method of forming SiGe-on-insulators.

The following example illustrates SiGe-on-insulator substrate materialsformed using the optimal implant, growing and thermal conditionsmentioned above.

EXAMPLE

In this example, SiGe-on-insulator substrate materials were fabricatedusing optimal conditions that fall within the ranges mentioned above.Table 1 indicates the initial samples, oxygen implant conditions (baseand second implants) and the thickness and Ge content of theGe-containing layer grown on top of the substrate prior to oxygenimplanting and heating. The heating step used in this example is asfollows:

-   -   ramp up from 1150° C. to 1300° C. at 0.5° C./min in 1.5% oxygen        (Ar dilution);    -   soak at 1300° C. for 2 hours;    -   ramp up to 1325° C. at 0.1° C./min in an ambient comprising        50.3% oxygen and 49.7% Ar;    -   soak at 1325° C. for 6 hours;    -   ramp down to 1200° C. at 0.5° C./min,    -   oxidize at 1200° C. for 3 hours in 40% oxygen; and    -   cool down.

Following these heating steps, the following steps were also performed:

-   -   (viii) Oxide removal in 10:1 (H₂O:HF) plus RCA-based wafer        cleaning.    -   (ix) Chemical-mechanical polishing and post-CMP clean    -   (x) Epitaxial growth of strained Si layer

TABLE 1 Original top layer SGOI BOX Final Ge thickness thicknessthickness fraction Relaxation (Δd/d)_(//) Ge loss Sample O⁺ Implant (Å)(Å) (Å) (%) (%) (%) (%) Process 2.1E17/169 1500 607 1031 12.2 73.3 0.33331 A keV; SiGe 2.5E15/159 (20%) keV Process 2.1E17/169 1000 596 115812.1 60.1 0.271 35 B keV; SiGe 2.5E15/159 (20%) keV

Table 1 also includes data for the final SGOI substrate material. Inparticular, the BOX thickness, Ge fraction, relaxation, (Δd/d)_(//)(which is the in-plane lattice parameter given in terms of % greaterthan Si), and Ge loss are provided in Table 1. The high relaxation andrelatively low Ge loss (˜30%) combined with the low defectivity (lessthan 10 stacking faults/cm²), excellent electrical buried oxideproperties (first mini-breakdown field greater than 6 MV/cm) and lowsurface roughness (3 Å RMS) of the substrates produced in the Examplemethod make them a suitable cost-effective substrate for use in CMOSmanufacturing. By reducing the ramping rates during steps (i), (iii) and(v) compared to the Example, the Ge loss was further reduced to 19%.

FIG. 6A shows a SEM cross-section (X-SEM) image of the Si/SGOI structureformed using the preferred embodiment in the Example (Process B) afterthe first ramp step to 1300° C. The buried oxide has been formed but itis thin and has a rough upper interface. FIG. 6B is a X-SEM image of thesame structure (Process B) as shown in FIG. 6A that has completed allthe thermal processing steps (through step viii). The role of steps(iii) and (iv) are clearly shown to both increase the thickness of theburied oxide layer and to sharpen the upper interface.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the scope and spirit ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A substrate material comprising: a Si-containing substrate; a buriedoxide that is resistant to Ge diffusion present atop said Si-containingsubstrate; and a substantially relaxed SiGe layer present atop saidburied oxide, wherein said substantially relaxed SiGe layer has asurface roughness of about 1.5 nm or less, and a crystal defect densityof about 5×10⁷/cm² or less.
 2. The substrate material of claim 1 furthercomprising a first strained Si-containing layer located atop thesubstantially relaxed SiGe layer.
 3. The substrate material of claim 2further comprising alternating layers of relaxed SiGe and strained Silocated atop the first strained Si-containing layer.
 4. The substratematerial of claim 1 further comprising a layer composed of at leastIII-V elements located atop the substantially relaxed SiGe layer.
 5. Thesubstrate material of claim 1 wherein said buried oxide has amini-breakdown field of about 6 MV/cm or greater.
 6. The substratematerial of claim 1 wherein said buried oxide is patterned orunpatterned.
 7. The substrate material of claim 1 wherein saidsubstantially relaxed SiGe layer has a measured lattice relaxation offrom about 1 to about 100%.
 8. A heterostructure comprising thesubstrate material of claim 1 and a strained Si layer formed atop thesubstantially relaxed SiGe layer.
 9. The heterostructure of claim 8wherein said buried oxide is patterned or unpatterned.
 10. Theheterostructure of claim 8 wherein said substantially relaxed SiGe layerhas a measured lattice relaxation of from about 1 to about 100%.
 11. Theheterostructure of claim 8 wherein said strained Si layer comprises anepi-Si layer.
 12. The heterostructure of claim 8 wherein alternatinglayers of relaxed SiGe and strained Si are formed atop said strained Silayer.
 13. The heterostructure of claim 8 wherein said strained Si layeris replaced with a lattice mismatched compound selected from the groupconsisting of GaAs and GaP.